1. Field of the Invention
The present invention relates to an electronic storage device and the control method thereof, more particularly to a non-volatile solid-state electronic storage device and the control method thereof.
2. Description of Related Art
NAND-type flash memory is widely used in consuming products to be served as storage media because of rapid access speed and high reliability. Conventional solid-state data storage devices are Solid-Stage Disk (SSD), USB Flash Drive (UFD), memory cards etc. In particular, NAND-Type Flash Memory is mainly served as storage media.
FIG. 1 is a function schematic chart of a solid-state disk. The solid-state disk 120 connects with a host system 100 through disk drive interface 130. A control unit 140 executes commands of the host system 100 through system interface 110 and writes data into a storage media 160 or reads data from the storage media 160 according to logical addresses appointed by the commands. For realizing this function, the control unit 140 must be equipped with logical-to-physical address mapping function and the solid-state disk 120 should be equipped with the storage media 160 for storing logical-to-physical Address Mapping Tables which record relationships between the logical addresses and physical addresses. Since the logical-to-physical address Mapping Table needs large storage space, for saving storage space to simplify the mapping program and decrease cost of the control unit 140, the physical storage space will be divided into many memory segments with equal or unequal contents. Each memory segment stores the logical-to-physical Address Mapping Table thereof. Please refer to FIG. 2, when the host system 100 sends commands for reading or writing data in particular logical addresses, the control unit 140 determines the physical memory segment to which the logical address belongs according to the logical-to-physical Address Mapping Table. If the logical-to-physical Address Mapping Table of the particular memory segment was not loaded into the memory unit 150 of the control unit 140, then an unused table which is originally stored in the control unit 140 will be written back to the memory media 160 and the table needed by the command will be loaded from the memory media 160.
If the addresses appointed by the commands of the host system 100 are sequential, that is the addresses range from large to small or from small to large, the access speed of the storage device will not be influenced seriously. However, when the addresses appointed by the commands of the host system 100 are not sequential, then different memory segments should be visited. Thus, the access speed of the storage device will be influenced seriously because the logical-to-physical address mapping tables should be switched frequently by writing back to the memory media 160 and reloaded to the control unit 140.
Although memory capacity of the control unit 140 can be increased for accommodating the mapping tables, and more than two mapping tables of the memory segments can be permitted to be visited at the same time for avoiding switching the mapping tables too frequently, the method is still restricted by the capacity of the memory unit 150 of the control unit 140. Hence, it is desirable to design an improved structure to address problems mentioned above.